The present invention relates to a semiconductor memory device, such as a flash memory, EEPROM, EPROM, PROM, ROM, or SRAM, which is arranged to improve a sense circuit that senses the potentials on bit lines and reduce parasitic capacitances associated with the bit lines to thereby allow fast data readout.
An example of a memory cell used in flash memories has an n-channel type of MOSFET cell used in flash memories has an n-channel type of MOSFET structure in which a charge storage layer (floating gate) and a control gate are stacked above a p-type semiconductor substrate.
Such a memory cell usually stores a bit of data, either "0" or "1", depending on the amount of charge stored on its floating gate. The stored data can be read out by applying a read voltage to the control gate and detecting the magnitude of resulting current flowing through the memory cell (hereinafter referred to as readout cell current).
For example, assume that positive charges are stored on the floating gate and the threshold voltage is set to less than 2 V. Then, a readout cell current is produced when a read voltage of 3 V is applied to the control gate, so that data "1" is read out. When negative charges are stored on the floating gate and the threshold voltage is more than 4 V, no cell current will be produced even if a read voltage of 3 V is applied to the control gate. In this case, read data is "0".
A number of memory cells are arranged in the form of a matrix to form a memory cell array. To read data out of a memory cell selected by an address signal, a sense amplifier is used as a sense circuit. To make a connection between a selected memory cell and the sense amplifier, a transmission gate is provided which is switched on or off by an address signal.
FIG. 1 shows in block diagram form a conventional flash memory.
A memory cell array is divided into two blocks 1-1 and 1-2. To apply a voltage at a predetermined level to a selected bit line (not shown), bit line select circuits 2-1 and 2-2 are disposed adjacent to the memory cell array blocks 1-1 and 1-2, respectively. A column address buffer 3 is provided which applies a column address signal to the bit line select circuits 2-1 and 2-2 to select a bit line in each memory cell array block.
The column address buffer 3 is arranged to output that column address signal in response to a block address signal indicating which memory cell array block to select. The block address signal is outputted from a block address buffer 4.
Data in a memory cell connected to a selected bit line is transferred over the bit line and a data transfer line 5 to a bit line control circuit 6 having a sense amplifier. The transferred cell data is amplified by the sense amplifier, buffered in a data input/output buffer 7, and outputted from a data input/output terminal 8 to the outside of the memory chip.
To-be-written input data applied to the data input/output terminal 8 is sent to the bit line control circuit 6 through the data input/output buffer 7. The bit line control circuit 6 outputs a bit line voltage corresponding to the input data onto the data transfer line 5, applying an input data-dependent voltage to a bit line selected by the bit line select circuit 2-1 or 2-2.
In each memory cell array block, though not shown, a plurality of word lines (for example, two word lines) forms one sector. To apply a voltage at a predetermined level to a selected sector of word lines, word line voltage transfer circuits 9-1 and 9-2 are disposed adjacent to the memory cell array blocks 1-1 and 1-2, respectively.
To select sectors having a sector address common to both the blocks, a sector select circuit 10 is provided in common to the blocks. A sector address signal is produced by a row address buffer 11 and applied to the sector select circuit 10. To select one word line from a sector selected by the sector select circuit 10, word line select circuits 12-1 and 12-2 are provided for the word line voltage transfer circuits 9-1 and 9-2, respectively.
The word line select circuits 12-1 and 12-2 receive a row address signal from the row address buffer 11 and a block address signal from the block address buffer 4. A voltage outputted from the word line select circuit 12-1 or 12-2 for a selected block is transferred to a selected sector via the corresponding word line voltage transfer circuit 9-1 or 9-2. The word line voltage control in the selected sector allows a word line to be selected from that sector. In addition, to select a source line in a selected block, source line select circuits 13-1 and 13-2 are provided each of which is also connected to receive a block address signal.
A voltage from the source line select circuit 13-1 or 13-2 for a selected block is sent to a selected sector. The source line voltage control in the selected sector allows a source line in that sector to be selected.
The row address buffer 11 is responsive to an address signal inputted from address signal input terminals 14 to provide a sector address signal and a row address signal. The column address buffer 3 and the block address buffer 4 are also connected to receive the address signal from the address signal input terminals to provide a block address signal and a column address signal.
The memory cell arrays 1-1 and 1-2, bit line select circuits 2-1 and 2-2, sector select circuit 10, word line voltage transfer circuits 9-1 and 9-2, select circuits 12-1 and 12-2, source line select circuits 13-1 and 13-2, row address buffer 11, block address buffer 4, bit line control circuit 6, data input/output buffer 7 and column address buffer 3 are each controlled by a control signal/control voltage generator 16, which is responsive to a control signal from a control signal input terminal 15 to provide control signals and control voltages.
In the memory thus arranged, at the time of a read operation data in a memory cell is transferred to the bit line control circuit 6 over a bit line and the data transfer line 5. The signal read from the memory cell is very small in magnitude. The fast detecting of this signal allows the reading speed to be increased. The capacitances associated with the bit lines are substantially equal to the capacitance associated with the data transfer line 5 or the latter may be larger than the former. If, therefore, the sense amplifier in the bit line control circuit 6 is placed in the vicinity of the bit lines, then the reading speed will be increased. In addition, if the sense amplifier, which is provided in common to many bit lines, is provided for each group of a smaller number of bit lines, the parasitic capacitance associated with each sense amplifier will be further reduced, allowing fast readout of data.
However, an increase in the number of sense amplifiers will result in an increase in the chip size. Therefore, it is desirable that each sense amplifier be of small dimensions and arranged to detect bit line signals with accuracy.
The sense amplifier in the bit line control circuit is heretofore placed apart from the memory cell array, requiring a relatively long data transfer line between the memory cell array and the sense amplifier. Thus, static capacitances associated with the transmission gates and the data transfer line become increased. With low readout cell currents, it takes long to read data.
The gate electrodes of memory cells arranged in the direction of a row form a word line. The longer the word line, the longer it takes to charge the word line up to a read voltage. This is a cause of long readout time.
Most of memory devices use a current mirror type of differential amplifier as a sense amplifier. This differential amplifier compares a readout cell current with a reference current to read data. Variations in operating characteristics between transistors forming the differential amplifier might cause a detection error in the magnitude relation between currents. To avoid this, it is required to make the difference between the cell current and the reference current large. However, an attempt to increase the readout cell current requires a quantity of charge to be stored on the cell floating gate to be increased, which increases the time taken to write into and erase the memory cell.
As described above, a conventional semiconductor memory device, such as a flash memory, has a problem that large stray capacitances associated with the bit lines result in an increase in the time taken to read data.
In addition, there is a problem that signal delays associated with the word lines result in an increase in the time taken to read data. Due to variations in operating characteristics among transistors constituting a sense amplifier in particular, readout cell currents have to be increased.